The present invention relates to failure localization and, more specifically, to prioritization metrics for efficient post-Si failure localization.
One of the most time consuming tasks in hardware (HW) verification processes is related to failure debug processing. The first stage of failure debug processing is failure localization and is mostly done manually and consumes significant time per each failing test. The task becomes especially challenging in post-Si verification processing, where knowledge of internal states is limited. Moreover, if the results of failure localization are incorrect or not sufficiently focused, the results can lead to wasted time and effort in subsequent debug processing based on failure location assumptions that are wrong.
Techniques have recently been developed for facilitating automation of failure localization processing and are often based on dynamic slicing techniques adopted from software (SW) debug domains. The techniques relate to simulations of tests on instruction-set simulators and build a dependency graph of the test instructions and resources. The techniques thus allow for automatic reporting of a set (or slice) of the test instructions that are related to the faulty resources at the end of the test.
The above-described techniques also incorporate justification heuristics that provide a reduced slice by filtering out instructions that are related to correct resources. However, the resulting slice still may still contain multiple instructions related to any faulty resource, without the ability to prioritize and further filter the findings.